Magnetic memory device

A magnetic memory device comprising:

• a substrate having an upper surface extending in a first horizontal direction and a second horizontal direction different from each other;
• a first semiconductor structure disposed on the substrate, and including a transistor and a second bonding pad;
• and
• a second semiconductor structure disposed on the first semiconductor structure, and including:
• a first bonding pad bonded to the second bonding pad;
• a memory structure disposed on the first bonding pad, electrically connected to the transistor, and including a first electrode layer in contact with the first bonding pad, a magnetic tunnel junction layer disposed on the first electrode layer, and a second electrode layer disposed on the magnetic tunnel junction layer;
• and
• a wiring disposed on the second electrode layer so as to be in contact with the second electrode layer,
• wherein each of a width in the first horizontal direction of the wiring and a width in the first horizontal direction of the first bonding pad decreases as each of the wiring and the first bonding pad extends toward the magnetic tunnel junction layer.

A magnetic memory device comprising:

• a substrate having an upper surface extending in a first horizontal direction and a second horizontal direction different from each other;
• a logic area including a first transistor disposed on the substrate, and a first lower bonding structure disposed on the first transistor;
• a memory cell area disposed on the logic area, and including:
• an upper bonding structure bonded to the first lower bonding structure,
• a memory structure disposed on the upper bonding structure and including a first electrode layer, a magnetic tunnel junction layer, and a second electrode layer sequentially stacked,
• a bit line disposed on the memory structure and connected to the second electrode layer,
• a capping film extending along a sidewall of the memory structure, and
• a mold insulating film disposed on the capping film so as to fill a space between the memory structures;
• and
• a peripheral circuit area disposed on the logic area and different from the memory cell area, and including a second transistor on the substrate and a second lower bonding structure disposed on the second transistor,
• wherein a width in the first horizontal direction of the memory structure decreases as the memory structure extends toward the upper surface of the substrate,
• wherein a width in the first horizontal direction of the mold insulating film increases as the mold insulating film extends toward the upper surface of the substrate.