Digit line formation in vertical three-dimensional (3d) memory
AssigneeMicron Technology, Inc.
InventorsBenben Li, Cheng Li
Life of this patent
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Abstract
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices include first source/drain regions and a second source/drain regions separated by channel regions. Gates at the channel regions formed fully around every surface of the channel region as gate-all-around (GAA) structures separated from channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes connected to the second source/drain regions and digit lines connected to the first source/drain regions.
Claims20
A method for forming arrays of memory cells, comprising:
- forming a stack having alternating layers of silicon germanium (SiGe) material and silicon (Si) material from a substrate;
- forming access devices in the stack and having respective gates formed at a different level from each other, wherein forming the access devices includes:
- forming a first opening through the stack and extending predominantly in a first direction;
- and
- forming a plurality of spaced columns adjacent to first source/drain regions of the access devices;
- forming storage nodes in the vertical stack;
- and
- forming, between the plurality of spaced columns, a plurality of spaced vertical digit lines that are electrically connected to the first source/drain regions.
A method for forming arrays of vertically stacked memory cells having horizontally oriented access devices and horizontally oriented storage nodes, comprising:
- forming a vertical stack having alternating layers of silicon germanium (SiGe) material and silicon (Si) material from a substrate;
- forming the horizontally oriented access devices in the vertical stack each having gates formed horizontally at a different level from each other, channel regions, first source/drain regions, and second source/drain regions separated by the channel regions, wherein forming the horizontally oriented access devices includes:
- forming a first vertical opening through the vertical stack and extending predominantly in a first horizontal direction;
- and
- depositing a sacrificial dielectric material in the first vertical opening to fill the first vertical opening;
- patterning a mask on a top surface of the vertical stack;
- selectively removing portions of the sacrificial dielectric material in the first vertical opening to form a plurality of spaced vertical openings;
- and
- depositing a selectively etchable dielectric fill material in the plurality of spaced vertical openings to form a plurality of spaced vertical columns adjacent to the first source/drain regions;
- forming horizontally oriented storage nodes in the vertical stack;
- and
- forming, between the plurality of spaced vertical columns, a plurality of spaced vertical digit lines that are electrically connected to the first source/drain regions.
A memory device, comprising:
- an array of vertically stacked memory cells having horizontally oriented access devices, and horizontally oriented storage nodes, wherein:
- the horizontally oriented access devices include channel regions, first source/drain regions, second source/drain regions separated by the channel regions, and gates on a gate dielectric material;
- and
- the horizontally oriented storage nodes are formed horizontally on the second source/drain regions of the horizontally oriented access devices;
- and
- vertical digit lines separated by a plurality of spaced vertical columns comprised of a selectively etchable dielectric fill material, wherein the vertical digit lines are connected to the first source/drain regions of the horizontally oriented access devices.
Dependencies are inferred from the claim text.