Semiconductor memory device and manufacturing method thereof
AssigneeSK hynix Inc.
InventorNam Jae LEE
Life of this patent
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Abstract
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.
Claims20
A semiconductor memory device comprising:
- a first etch stop layer;
- a source layer on the first etch stop layer;
- a second etch stop layer on the source layer;
- a stack structure on the second etch stop layer;
- and
- a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer,
- a bit line disposed over the channel structure;
- and
- a peripheral circuit structure disposed over the bit line and the peripheral circuit structure including a transistor,
- wherein a material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.
A semiconductor memory device comprising:
- a base part;
- a first etch stop layer on the base part;
- a source layer on the first etch stop layer;
- a second etch stop layer on the source layer;
- a stack structure on the second etch stop layer;
- a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure,
- a bit line disposed over the channel structure;
- and
- a peripheral circuit structure disposed over the bit line and the peripheral circuit structure including a transistor,
- wherein the channel structure is electrically connected to the source layer, and
- wherein a lowermost portion of the channel structure is disposed in the base part.
A semiconductor memory device comprising:
- a first base part;
- a first etch stop layer disposed over the first base part;
- a source layer disposed over the first etch stop layer;
- a second etch stop layer disposed over the source layer;
- a first stack structure disposed over the second etch stop layer and the first stack including first conductive patterns and first insulating patterns alternately stacked;
- a first channel structure penetrating the first and second etch stop layers, the first source layer, and the first stack structure;
- a first bit line disposed over the first channel structure;
- and
- a first bonding pattern connected to the first bit line,
- wherein the first channel structure is electrically connected to the first source layer, and
- wherein a lowermost portion of the first channel structure is disposed in the first base part.
Dependencies are inferred from the claim text.