Lin commander recessive state level detection

A network node of a LIN bus system comprising:

• a supply terminal (VS1) configured to receive a supply voltage;
• a bus terminal (BUS1) configured to receive a data signal (VBUS) representing serial data via a data line (LDAT), the data signal (VBUS) being a binary signal having high and low signal levels;
• a controllable voltage source (Q1) coupled to the supply terminal (VS1), the voltage source (Q1) being configured to output a voltage signal (VQ1);
• a receiver circuit including a comparator (K1) that is configured to compare the data signal (VBUS) with a reference signal (VREF), wherein the comparator (K1) generates a binary output signal (VRX) representing the result of the comparison, wherein the reference signal (VREF) is based on the voltage signal (VQ1);
• and
• a controller circuit comprising:
• a register that is configured to store at least one digital value (dSTORE), and
• a digital-to-analog converter, DAC, that is coupled to the register and configured to output a voltage level (VSTORE) based on the stored digital value (dSTORE),
• wherein the controller circuit is coupled to the voltage source (Q1) and configured to adjust the voltage signal (VQ1) based on the voltage level (VSTORE1).