Coherent key management across multiple chiplets

An electronic device, comprising:

• a memory system comprising instructions;
• and
• a processor system coupled to the memory system, the processor system including a plurality of chiplets, wherein the processor system is configured to:
• mutually authenticate, by a first chiplet root of trust (C-RoT) of a first chiplet and a second C-RoT of a second chiplet of the plurality of chiplets, the first chiplet and the second chiplet;
• based on the mutual authentication of the first chiplet and the second chiplet, provision a common pairing key to the first C-RoT and the second C-RoT to establish a common security boundary across the first chiplet and the second chiplet;
• provision, to the first chiplet, a first chiplet base key that is specific to the first chiplet;
• provision, to the second chiplet, a second chiplet base key that is specific to the second chiplet;
• derive, using the first chiplet base key, a first chiplet-specific key for a first chiplet-specific function;
• and
• perform chiplet attestation for the first chiplet based on the first chiplet-specific key.