Digital Phase-Locked Loop Circuitry

A method of operating phase-locked loop (PLL) circuitry, comprising:

• generating, using a digitally controlled oscillator (DCO), an output clock signal;
• generating, using a frequency divider, a feedback clock signal based on the output clock signal and a division ratio;
• and
• locking the PLL circuitry by adjusting, using a sigma delta modulator (SDM), the division ratio according to a channel word that has been corrected based on a phase error of the feedback clock signal, wherein the DCO generates the output clock signal based on a digital control signal that remains at a constant value while the PLL circuitry locks.

Circuitry comprising:

• a digitally controlled oscillator (DCO) configured to generate an output clock signal;
• a frequency divider configured to generate a feedback clock signal based on the output clock signal and a division ratio;
• a sigma delta modulator (SDM) communicatively coupled to an input of the frequency divider;
• and
• a loop filter communicatively coupled between an output of the frequency divider and an input of the SDM, wherein
• the loop filter is configured to generate a filtered phase error signal based on the feedback clock signal and a reference clock signal, and
• the SDM is configured to adjust the division ratio of the frequency divider based on the filtered phase error signal.