Multi-port memory testing using concurrent operations

One or more computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method comprising:

• creating, in a circuit design, a memory-testing circuit configured to perform a test on one or more memories in the circuit design, each of the one or more memories having a plurality of logical ports, the plurality of logical ports being divided into a plurality of test ports, each of the plurality of test ports being capable of both write and read operations and comprising one or two logical ports, the memory-testing circuit comprising:
• a test algorithm control unit configured to implement a test algorithm, the test algorithm comprising a sequence of read and write operations, each execution of the test algorithm performing a memory test through one of the plurality of test ports, one logical port in the test port under test configured to receive an algorithm command corresponding to one read operation or one write operation in the sequence of read and write operations, logical ports that are not receiving the algorithm command configured to receive concurrent commands generated based on the test algorithm;
• a reference address generator configured to generate, based on the test algorithm, a reference address for the one logical port in the test port under test;
• one or more concurrent address generators configured to generate, based on the reference address, one or more concurrent addresses for the logical ports that receive the concurrent commands;
• a test port counter configured to increment after each execution of the test algorithm and generate a test port count signal;
• and
• address selecting circuitry for each of the one or more memories configured to select, based on an address selection signal, the reference address or one of the one or more concurrent addresses for each of the plurality of logical ports, the address selection signal being generated based on the test port count signal.