Data latch circuit and semiconductor device
AssigneeKioxia Corporation
InventorHiromitsu KOMAI
Life of this patent
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Abstract
A data latch circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor. The second transistor has its current path connected at one end to a first potential node having a first potential, and connected at another end to the first node. The fifth transistor has its current path connected at one end to a second node, and connected at another end to a second potential node. When the second transistor is off, a leakage current corresponding to a potential difference between the first potential node and the first node occurs in the second transistor. When the fifth transistor is off, a leakage current corresponding to a potential difference between the second node and the second potential node occurs in the fifth transistor.
Claims16
A data latch circuit comprising:
- a first transistor, a current path of which is connected at one end to a first node, and connected at another end to a first bus;
- a second transistor, a current path of which is connected at one end to a first potential node having a first potential, and connected at another end to the first node;
- a third transistor, a current path of which is connected at one end to the first node, and connected at another end to a second potential node having a second potential lower than the first potential, a gate of the third transistor being connected to a second node;
- a fourth transistor, a current path of which is connected at one end to the first potential node, and connected at another end to the second node, a gate of the fourth transistor being connected to the first node;
- and
- a fifth transistor, a current path of which is connected at one end to the second node, and connected at another end to the second potential node,
- wherein when the second transistor is off, a leakage current corresponding to a potential difference between the first potential node and the first node occurs in the second transistor, and
- when the fifth transistor is off, a leakage current corresponding to a potential difference between the second node and the second potential node occurs in the fifth transistor.
A semiconductor device comprising:
- a first data latch circuit configured to hold data in at least one of a first node and a second node;
- and
- a control unit configured to control the first data latch circuit, wherein the first data latch circuit includes;
- a first transistor, a current path of which is connected at one end to the first node, and connected at another end to a first bus,
- a second transistor, a current path of which is connected at one end to a first potential node having a first potential, and connected at another end to the first node,
- a third transistor, a current path of which is connected at one end to the first node, and connected at another end to a second potential node having a second potential lower than the first potential, a gate of the third transistor being connected to the second node,
- a fourth transistor, a current path of which is connected at one end to the first potential node, and connected at another end to the second node, a gate of the fourth transistor being connected to the first node, and
- a fifth transistor, a current path of which is connected at one end to the second node, and connected at another end to the second potential node, and
- when the second transistor is off, a leakage current corresponding to a potential difference between the first potential node and the first node occurs in the second transistor, and
- when the fifth transistor is off, a leakage current corresponding to a potential difference between the second node and the second potential node occurs in the fifth transistor.
Dependencies are inferred from the claim text.