In-memory computation circuit using static random access memory (sram) array segmentation and local compute tile read based on weighted current

An in-memory computation circuit configured to perform an in-memory compute operation multiplying weight data by feature data to generate a decision for the in-memory compute operation, comprising:

• a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a bit line connected to the memory cells of the column, said memory cells configured to store bits of the weight data for the in-memory compute operation;
• a word line driver circuit for each row having an output connected to drive the word line of the row;
• a row controller circuit configured to simultaneously actuate at least one word line for each sub-array for the in-memory compute operation by applying pulses through the word line driver circuits to the word lines;
• and
• a computation tile circuit for each sub-array, wherein each computation tile circuit includes a plurality of column compute circuits coupled to the bit lines, respectively, of the columns of the sub-array;
• wherein each column compute circuit comprises:
• a circuit configured to generate a first gate control signal in response to a bit of the weight data on the bit line;
• a first MOS transistor having a source coupled to a power supply node, a gate configured to receive the first gate control signal and a drain;
• a second MOS transistor having a source coupled to the drain of the first MOS transistor, a gate configured to receive a second gate control signal, and a drain configured to output a drain current having a magnitude dependent on a voltage of the second gate control signal;
• an integration circuit configured to integrate the drain current and generate an output signal;
• and
• a multiplexer having a first input configured to receive a first voltage, a second input configured to receive a second voltage different from the first voltage, and a third input configured to receive a third voltage different from the first and second voltages, and wherein the multiplexer is configured to select one of the first, second and third voltages for output as the voltage for the second gate control signal in response to the feature data for the in-memory compute operation.