Semiconductor device

A semiconductor device comprising:

• a power management portion, a setting information retention portion, a power switch portion, a data retention portion, and a backup portion,
• wherein the power management portion and the data retention portion are provided in a first layer,
• wherein the setting information retention portion, the power switch portion, and the backup portion are provided in a second layer over the first layer,
• wherein the data retention portion is configured to retain data,
• wherein the power management portion is configured to supply an instruction for controlling power gating to the power switch portion and to supply, to the setting information retention portion, setting information indicating whether to block power supply to the data retention portion by the power gating,
• wherein the setting information retention portion comprises a first transistor and a first capacitor,
• wherein one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor,
• wherein a first potential based on the setting information supplied from the power management portion is supplied to the other of the source and the drain of the first transistor,
• wherein a signal which controls a conduction state of the first transistor is supplied from the power management portion to a gate of the first transistor,
• wherein a second potential corresponding to the first potential is retained in the one terminal of the first capacitor,
• wherein the power switch portion comprises a second transistor and a third transistor,
• wherein a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor,
• wherein one of a source and a drain of the second transistor is electrically connected to a first wiring through which a third potential is supplied,
• wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring for supplying a fourth potential corresponding to the third potential to the data retention portion,
• wherein a signal based on the instruction is supplied to the other of the source and the drain of the third transistor,
• wherein a signal based on the second potential is supplied to a gate of the third transistor,
• wherein the backup portion comprises a fourth transistor, a fifth transistor, and a second capacitor,
• wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor and one terminal of the second capacitor,
• wherein the other of the source and the drain of the fourth transistor is electrically connected to the data retention portion through a third wiring,
• wherein the other of the source and the drain of the fifth transistor is electrically connected to the data retention portion through a fourth wiring,
• wherein a signal which controls a conduction state of the fourth transistor is supplied from the power management portion to a gate of the fourth transistor,
• wherein a signal which controls a conduction state of the fifth transistor is supplied from the power management portion to a gate of the fifth transistor, and
• wherein a fifth potential corresponding to the data is retained in the one terminal of the second capacitor.

A semiconductor device comprising:

• a power management portion, a setting information retention portion, a power switch portion, a data retention portion, and a backup portion,
• wherein the power management portion, the power switch portion, and the data retention portion are provided in a first layer,
• wherein the setting information retention portion and the backup portion are provided in a second layer over the first layer,
• wherein the data retention portion is configured to retain data,
• wherein the power management portion is configured to supply an instruction for controlling power gating to the power switch portion and to supply, to the setting information retention portion, setting information indicating whether to block power supply to the data retention portion by the power gating,
• wherein the setting information retention portion is configured to retain the setting information supplied from the power management portion,
• wherein the power switch portion is configured to switch whether to block power supply to the data retention portion on the basis of the instruction and the setting information retained in the setting information retention portion, and
• wherein the backup portion is configured to store and retain the data on the basis of a signal supplied from the power management portion.

A semiconductor device comprising:

• a power management portion, a setting information retention portion, a power switch portion, a data retention portion, and a backup portion,
• wherein the power management portion, the power switch portion, and the data retention portion are provided in a first layer,
• wherein the setting information retention portion and the backup portion are provided in a second layer over the first layer,
• wherein the data retention portion is configured to retain data,
• wherein the power management portion is configured to supply an instruction for controlling power gating to the power switch portion and to supply, to the setting information retention portion, setting information indicating whether to block power supply to the data retention portion by the power gating,
• wherein the setting information retention portion comprises a first transistor and a first capacitor,
• wherein one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor,
• wherein a first potential based on the setting information supplied from the power management portion is supplied to the other of the source and the drain of the first transistor,
• wherein a signal which controls a conduction state of the first transistor is supplied from the power management portion to a gate of the first transistor,
• wherein a second potential corresponding to the first potential is retained in the one terminal of the first capacitor,
• wherein the power switch portion comprises a second transistor and a third transistor,
• wherein a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor,
• wherein one of a source and a drain of the second transistor is electrically connected to a first wiring through which a third potential is supplied,
• wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring for supplying a fourth potential corresponding to the third potential to the data retention portion,
• wherein a signal based on the instruction is supplied to the other of the source and the drain of the third transistor,
• wherein a signal based on the second potential is supplied to a gate of the third transistor,
• wherein the backup portion comprises a fourth transistor, a fifth transistor, and a second capacitor,
• wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor and one terminal of the second capacitor,
• wherein the other of the source and the drain of the fourth transistor is electrically connected to the data retention portion through a third wiring,
• wherein the other of the source and the drain of the fifth transistor is electrically connected to the data retention portion through a fourth wiring,
• wherein a signal which controls a conduction state of the fourth transistor is supplied from the power management portion to a gate of the fourth transistor,
• wherein a signal which controls a conduction state of the fifth transistor is supplied from the power management portion to a gate of the fifth transistor, and
• wherein a fifth potential corresponding to the data is retained in the one terminal of the second capacitor.