Semiconductor device capable of switching operation voltage

An apparatus comprising:

• a first external power supply line supplied with a first external power voltage;
• a second external power supply line supplied with a second external power voltage lower than the first external power voltage;
• a third external power supply line supplied with a third external power voltage lower than the second external power voltage;
• an internal power supply line;
• a first power switch coupled between the first external power supply line and the first internal power supply line;
• a second power switch coupled between the second external power supply line and the first internal power supply line;
• and
• a pull-down circuit coupled between the internal power supply line and the third external power supply line,
• wherein the first power switch is configured to be changed from an OFF state to an ON state after the second power switch is changed from an ON state to an OFF state, and
• wherein the pull-down circuit is configured to be activated for a part of a time period after the second power switch is changed to an OFF state and before the first power switch is changed to an ON state.

An apparatus comprising:

• a first power supply line supplied with a first power voltage;
• a second power supply line supplied with a second power voltage different from the first power voltage;
• first, second, and third transistors coupled in series between the first power supply line and the second power supply line;
• a first comparator circuit configured to control the first transistor;
• a second comparator circuit configured to control the third transistor;
• and
• a load circuit configured to operate on a voltage appearing at a source of the second transistor,
• wherein the first transistor has a first conductivity type,
• wherein the second and third transistors have a second conductivity type opposite to the first conductivity type,
• wherein the second transistor is configured to be controlled by a control signal,
• wherein the first comparator circuit has a first input node supplied with a reference voltage, a second input node coupled to a drain of the first transistor, and an output node coupled to a control electrode of the first transistor,
• wherein the second comparator circuit has a first input node supplied with the reference voltage, a second input node coupled to the source of the second transistor, and an output node coupled to a control electrode of the third transistor such that the second comparator circuit is configured to bring the third transistor into an ON state when the voltage appearing at the source of the second transistor is higher than the reference voltage, and
• wherein the second comparator circuit is configured to be activated before the control signal is activated.