Memory system performing self-refresh operation

A memory device comprising:

• a base die configured to output a temperature code signal after a start of a self-refresh operation;
• and
• a core die comprising first and second channels,
• wherein the first channel is configured to generate a first refresh code signal that is set as a gray code based on the temperature code signal, perform the self-refresh operation based on a first refresh pulse signal having a generation cycle adjusted based on a combination of logic levels of the first refresh code signal, and adjust the generation cycle of the first refresh pulse signal by latching the first refresh code signal in synchronization with the first refresh pulse signal, and
• wherein the second channel is configured to generate a second refresh code signal that is set as a gray code based on the temperature code signal, perform the self-refresh operation based on a second refresh pulse signal having a generation cycle adjusted based on a combination of logic levels of the second refresh code signal, and adjust the generation cycle of the second refresh pulse signal by latching the second refresh code signal in synchronization with the second refresh pulse signal.

A memory device comprising:

• a base die configured to output a temperature code signal after a start of a self-refresh operation;
• and
• a core die comprising first and second channels,
• wherein the first channel is configured to generate a refresh code signal that is set as a gray code based on the temperature code signal, perform the self-refresh operation based on a first refresh pulse signal having a generation cycle adjusted based on a combination of logic levels of the refresh code signal, and adjust the generation cycle of the first refresh pulse signal by latching the refresh code signal in synchronization with the first refresh pulse signal, and
• wherein the second channel is configured to receive the refresh code signal from the first channel, perform the self-refresh operation based on a second refresh pulse signal having a generation cycle adjusted based on a combination of logic levels of the refresh code signal, and adjust the generation cycle of the second refresh pulse signal by latching the refresh code signal in synchronization with the second refresh pulse signal.