Gain cell memory device using enhanced sensing scheme and methods for operating the same

A gain cell memory device structure comprising:

• a write transistor located on a substrate;
• a read transistor located on the substrate;
• an additional read transistor located on the substrate and connected in series with the read transistor;
• a capacitor comprising a first electrode, a node dielectric, and a second electrode, wherein the first electrode is electrically connected to a first source/drain region of the write transistor and to a gate electrode of the read transistor;
• dielectric material layers overlying the transistors, wherein the capacitor is embedded within the dielectric material layers;
• a read bit line electrically connected to a drain region of the additional read transistor;
• a source bias line electrically connected to a source region of the read transistor;
• and
• a peripheral circuit configured to apply a current-boost source bias voltage to the source bias line during read operations, thereby enhancing read margin through increased on-current while preserving overall device efficiency and reducing the need for frequent refresh operations, wherein the peripheral circuit applies a pre-charge bias voltage to the read bit line prior to turning on the additional read transistor and measures voltage after a pre-charge step.

A method of operating a gain cell memory device structure comprising:

• providing a substrate having a write transistor and a read transistor located thereon, and a capacitor embedded within overlying dielectric material layers, wherein a first electrode of the capacitor is electrically connected to a first source/drain region of the write transistor and to a gate electrode of the read transistor;
• applying a write bias voltage to a second source/drain region of the write transistor while turning on the write transistor to encode a data bit in the first electrode;
• pre-charging a read bit line electrically connected to a drain region of the read transistor at a pre-charge bias voltage;
• applying a current-boost source bias voltage to a source bias line electrically connected to a source region of the read transistor;
• and
• sensing a voltage at the drain region of the read transistor, thereby differentiating charge states in the capacitor with improved accuracy and reduced error rates while extending retention time, wherein a magnitude of a difference between the pre-charge bias voltage and the current-boost source bias voltage is greater than between the pre-charge bias voltage and a normal source bias voltage.