Application processor, electronic device having the same, and method of operating the same

A method of operating an application processor, comprising:

• determining, by a display video timer and a PLL sleep control logic included in the application processor, whether data transmission is present;
• determining, by the PLL sleep control logic, whether to enter a low power mode when no data transmission is present;
• selecting, by the display video timer or an always-on video timer, one of a plurality of low power modes based on a frame update interval;
• and controlling, by the PLL sleep control logic, a clock switching logic, a PLL wake-up generation logic, and a PLL, entry into a selected low power mode, wherein the plurality of low power modes include a PLL sleep mode, a ULPS mode, and a power-off mode.

A method of operating an application processor, comprising:

• receiving a low power mode entry request signal from a display driver integrated circuit (DDI);
• entering a dynamic refresh rate (DRR) mode in response to the low power mode entry request signal;
• entering, during the DRR mode, a selected low power mode among a plurality of low power modes in a stepwise manner;
• and exiting the selected low power mode and transmitting a new frame to the display driver integrated circuit in response to a synchronization signal when a frame update is required.