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US 2026/0267936 A1Published application
Pipeline architecture for real-valued fast fourier transform (fft) calculations
AssigneeQUALCOMM Incorporated
InventorsIsmail DEMIRKAN, Xiao JIN, James ZHANG
Life of this patent
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Abstract
A method of pipeline relaxation for real-valued fast Fourier transform (FFT) processing includes determining idle cycles in stages of one or more pipelines for an FFT calculation. The method also includes reordering selected operations in the one or more pipelines to perform the selected operations during the idle cycles in the stages.
Claims16
A method of pipeline relaxation for real-valued fast Fourier transform (FFT) processing, comprising:
- determining idle cycles in a plurality of stages of at least one pipeline for an FFT calculation;
- and
- reordering selected operations in the at least one pipeline to perform the selected operations during the idle cycles in the plurality of stages.
An apparatus, comprising:
- a memory;
- and
- at least one processor coupled to the memory, the at least one processor configured:
- to determine idle cycles in a plurality of stages of at least one pipeline for an FFT calculation;
- and
- to reorder selected operations in the at least one pipeline to perform the selected operations during the idle cycles in the plurality of stages.
3 more elements
An apparatus, comprising:
- means for determining idle cycles in a plurality of stages of at least one pipeline for an FFT calculation;
- and
- means for reordering selected operations in the at least one pipeline to perform the selected operations during the idle cycles in the plurality of stages.
-20. (canceled)
Dependencies are inferred from the claim text.