Using spare cores for mitigation of hardware problems

A system comprising:

• multiple processing cores;
• storage having instructions;
• and
• hardware resources shared by the multiple processing cores, wherein the instructions, when executed by respective processing cores, cause the system to:
• execute workloads on two or more processing cores of the system, the workloads including a first workload that executes on a first processing core of the system and a second workload that executes on a second processing core of the system;
• and
• execute a hardware mitigation algorithm on an available third processing core, the hardware mitigation algorithm comprising:
• detecting a hardware state of one or more individual hardware resources utilized by the first processing core and the second processing core;
• comparing the detected hardware state to one or more fault criteria for initiating a hardware mitigation action;
• and
• when the detected hardware state matches the one or more fault criteria, performing the hardware mitigation action by the third processing core,
• wherein the hardware mitigation action changes state of the one or more individual hardware resources.

A computer-readable storage medium storing instructions which, when executed by a processing device, cause the processing device to perform acts comprising:

• executing workloads on processing cores of a system, the workloads including a first workload that executes on a first processing core of the system and a second workload that executes on a second processing core of the system;
• and
• executing a hardware mitigation algorithm on a third processing core, the hardware mitigation algorithm comprising:
• detecting a hardware state of one or more hardware resources utilized by the first processing core and the second processing core;
• comparing the detected hardware state to one or more fault criteria for initiating a hardware mitigation action;
• and
• when the detected hardware state matches the one or more fault criteria, performing the hardware mitigation action by the third processing core,
• wherein the hardware mitigation action changes state of the one or more hardware resources.