Low-power operations using leading zero count
AssigneeApple Inc.
InventorsFatemeh KASHFI, Michael L. LIU, Joseph RABINOWICZ
Life of this patent
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Abstract
An arithmetic-compare circuit that includes a first logic circuit and a second logic circuit is disclosed. The first logic circuit may perform an arithmetic-compare operation using a first operand, a second operand, and a third operand. The second logic circuit may determine respective leading-zero counts for the first operand, the second operand and the third operand, and predict a result of the arithmetic-compare operation using the respective leading zero counts. The first logic circuit may be disabled based on the predicted result.
Claims20
An apparatus, comprising:
- a first logic circuit configured to:
- determine respective leading-zero counts for a first operand, a second operand and a third operand;
- and
- predict, using the respective leading-zero counts for the first operand, the second operand, and the third operand, a first result of an arithmetic-compare operation;
- and
- a second logic circuit configured to disable, using the first result, an execution of the arithmetic-compare operation.
A method, comprising:
- receiving, by an arithmetic-compare circuit, a first operand, a second operand, and a third operand, wherein the arithmetic-compare circuit includes a first logic circuit and a second logic circuit;
- determining, by the first logic circuit, respective leading-zero counts for the first operand, the second operand, and the third operand;
- generating, by the first logic circuit, a prediction of a first result of an arithmetic-compare operation using the respective leading-zero counts;
- disabling, by the second logic circuit, an execution of the arithmetic-compare operation based on the prediction;
- and
- generating, by the arithmetic-compare circuit, a final result using the prediction.
An apparatus, comprising:
- a first logic circuit configured to:
- determine respective signs of a first operand, a second operand and a third operand;
- and
- predict, using a first sign of the first operand and a second sign of the second operand, a sign of an arithmetic portion of an arithmetic-compare operation;
- perform a comparison of the sign of the arithmetic portion of the arithmetic-compare operation and a third sign of the third operand;
- and
- a second logic circuit configured to disable, using a result of the comparison, an execution of the arithmetic-compare operation.
Dependencies are inferred from the claim text.