Techniques to manage data sharing for a multi-core processor
AssigneeIntel Corporation
InventorsAyan MANDAL, Priyanka SINGLA, Neetu JINDAL, Leon POLISHUK
Life of this patent
Estimating the term…
Abstract
Examples include techniques to manage data sharing for a multi-core processor. The examples include use of a data sharing counter value to determine whether to cause a last level cache (LLC) slice allocated to a core of the multi-core processor to be placed in an inclusive or non-inclusive mode for other cores of the multi-core processor to access data loaded to the LLC slice.
Claims20
An apparatus comprising:
- a core of a multi-core processor, the core to be configured to cause a request to load data from system memory to a last level cache (LLC) slice allocated to the core, the LLC slice included in a cache shared with at least one other core of the multi-core processor, the data to be shared between the core and the at least one other core in association with execution of an application workload, wherein the core includes circuitry configured to:
- maintain a data sharing count value;
- cause the data sharing count value to be decremented by a first decrement value responsive to detecting the request to load the data from system memory;
- and
- cause the LLC slice to be placed in an inclusive or non-inclusive mode for the data loaded to the LLC slice based on whether the decremented data sharing count value exceeds a threshold count value.
At least one machine readable medium comprising a plurality of instructions that in response to being executed by circuitry located at or with a core of a multi-core processor, causes the circuitry to:
- maintain a data sharing count value for data loaded from system memory to a last level cache (LLC) slice allocated to the core, the LLC slice included in a cache shared with at least one other core of the multi-core processor, the data to be shared between the core and the at least one other core in association with execution of an application workload;
- decrement, by a first decrement value, the data sharing count value responsive to detecting a request from the core to load the data from system memory to the LLC slice;
- and
- cause the LLC slice to be placed in an inclusive or non-inclusive mode for the data loaded to the LLC slice based on whether the decremented data sharing count value exceeds a threshold count value.
A system comprising:
- a coherency compute fabric to include a shared cache, the shared cache to include a plurality of last level cache (LLC) slices separately allocated to individual cores from among a plurality of cores of a core cluster;
- and
- a core from among the plurality of cores, the core to be configured to cause a request to load data from system memory to an LLC slice from among the plurality of LLC slices that is allocated to the core, the data to be shared between the core and at least one other core from among the plurality of cores of the core cluster, the data to be shared in association with execution of an application workload, wherein the core includes circuitry configured to:
- maintain a data sharing count value;
- cause the data sharing count value to be decremented by a first decrement value responsive to detecting the request to load the data from system memory;
- and
- cause the LLC slice to be placed in an inclusive or non-inclusive mode for the data loaded to the LLC slice based on whether the decremented data sharing count value exceeds a threshold count value.
Dependencies are inferred from the claim text.