US 2026/0266903 A1Published application

Configurable test circuit

AssigneeHewlett Packard Enterprise Development LP

InventorsCurtis Love Purnell, Mujeeb Rehman

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Abstract

According to an implementation, a configurable test circuit enables identical host processor motherboards to support Joint Test Action Group (JTAG) debugging across multiple operating configurations. Each motherboard includes a processor socket, a JTAG header, a transceiver coupled between the JTAG header and processor socket, multiplexers coupled between the processor socket and a connector interface, and a control circuit. In a single processor configuration, JTAG signals route from the header through the processor socket and return to the header. In a dual processor configuration, two identical motherboards couple through their connector interfaces, where one processor functions as a bootstrap processor (BSP) while the other operates as an application processor (AP). The control circuit configures the multiplexers to create a debug chain from the BSP motherboard's JTAG header through both processors.

Claims20

Dependent claims

A computer system comprising a first host processor motherboard couplable to a second host processor motherboard, each host processor motherboard comprising:

a processor socket;
a connector interface configured to couple the first host processor motherboard to the second host processor motherboard;
a Joint Test Action Group (JTAG) header;
a transceiver coupled between the JTAG header and the processor socket;
a first multiplexer coupled between the transceiver and the connector interface;
a plurality of switches coupled to the processor socket;
a set of multiplexers coupled between the plurality of switches and the JTAG header and between the plurality of switches and the connector interface;
and
a control circuit configured to control the routing of signals through the transceiver, the first multiplexer, the plurality of switches, and the set of multiplexers,
wherein in a first operating mode, the control circuit is configured to:
route JTAG signals from the JTAG header of the first host processor motherboard through both processor sockets,
route test data input signals from the JTAG header of the first host processor motherboard to the processor socket of the first host processor motherboard,
route test data output signals of the processor socket of the first host processor motherboard as test data input signals to the processor socket of the second host processor motherboard, and
route test data output signals of the processor socket of the second host processor motherboard to the JTAG header of the first host processor motherboard.

11 more elements

A non-transitory computer-readable medium storing instructions for operating a host processor motherboard that, when executed by a control circuit, cause the control circuit to:

detect an operating mode of the host processor motherboard;
configure a transceiver coupled between a Joint Test Action Group (JTAG) header and a processor socket;
configure a first multiplexer coupled between the transceiver and a connector interface;
configure a plurality of switches coupled to the processor socket;
and
configure a set of multiplexers coupled between the plurality of switches and the JTAG header and between the plurality of switches and the connector interface,
wherein, in a first operating mode, the instructions cause the control circuit to:
route JTAG signals from the JTAG header through both the processor socket and a processor socket of a second host processor motherboard,
route test data input signals from the JTAG header to the processor socket,
route test data output signals of the processor socket as test data input signals to the processor socket of the second host processor motherboard, and
route test data output signals of the processor socket of the second host processor motherboard to the JTAG header.

8 more elements

A method for operating a host processor motherboard, the method comprising:

detecting an operating mode of the host processor motherboard;
configuring a transceiver coupled between a Joint Test Action Group (JTAG) header and a processor socket;
configuring a first multiplexer coupled between the transceiver and a connector interface;
configuring a plurality of switches coupled to the processor socket;
and
configuring a set of multiplexers coupled between the plurality of switches and the JTAG header and between the plurality of switches and the connector interface,
wherein, in a first operating mode, the method comprises:
routing JTAG signals from the JTAG header through both the processor socket and a processor socket of a second host processor motherboard,
routing test data input signals from the JTAG header to the processor socket,
routing test data output signals of the processor socket as test data input signals to the processor socket of the second host processor motherboard, and
routing test data output signals of the processor socket of the second host processor motherboard to the JTAG header.

8 more elements

Dependencies are inferred from the claim text.