US 2026/0262552 A1Published application

A system-in-package structure and method for manufacturing same

AssigneeSJ Semiconductor(Jiangyin) Corporation

InventorsYenheng CHEN, Chengchung LIN

Life of this patent

Estimating the term…

Loading patent…

Abstract

The present disclosure provides a system-in-package (SiP) structure and a method for manufacturing it. The structure includes: a redistribution layer (RDL), TSV bridging substrates, first-type chips, second-type chips, a first molding compound layer, PCB substrates, third-type chips, and a second molding compound layer; the TSV bridging substrates and the first-type chips are directly bonded to an upper surface of the redistribution layer; the second-type chips are bonded to an upper surface of the TSV bridging substrates; the PCB substrates are bonded to a lower surface of the redistribution layer; the third-type chips are bonded to a lower surface of the PCB substrates. The system-in-package structure and method for manufacturing the same provided by the present disclosure address the issues in conventional packaging technologies, such as high structural cost, low process yield, and the need to go through multiple levels of different manufacturing facilities during fabrication, which hinders rapid product development.

Claims11

Dependent claims

A method for manufacturing a system-in-package (SiP) structure, comprising:

S1. providing a temporary carrier and forming a redistribution layer on an upper surface of the temporary carrier;
S2. providing one or more TSV bridging substrates and one or more first-type chips, and bonding the TSV bridging substrates and the first-type chips to an upper surface of the redistribution layer, respectively;
S3. providing one or more second-type chips, and bonding the second-type chips to the upper surface of the TSV bridging substrates, wherein a solder bump pitch of the second-type chips is higher than a solder bump pitch of the first-type chips;
S4. forming a first molding compound layer on an upper surface of the redistribution layer, wherein the first molding compound layer encapsulates the first-type chips and the second-type chips;
S5. removing the temporary carrier, providing a plurality of PCB substrates, and bonding the plurality of PCB substrates to a lower surface of the redistribution layer;
S6. providing a plurality of third-type chips, and bonding the plurality of third-type chips to the plurality of PCB substrates, wherein the solder bump pitch of the third-type chips is lower than the solder bump pitch of the first-type chips;
and
S7. forming a second molding compound layer over the lower surface of the redistribution layer, wherein the second molding compound layer encapsulates the plurality of third-type chips.

5 more elements

A SiP structure, wherein the structure comprises:

a redistribution layer, one or more TSV bridging substrates, one or more first-type chips, one or more second-type chips, a first molding compound layer, a plurality of PCB substrates, a plurality of third-type chips, and a second molding compound layer;
wherein a solder bump pitch of the first-type chips is lower than a solder bump pitch of the second-type chips but higher than that of the third-type chips;
wherein the TSV bridging substrates and the first-type chips are directly bonded to an upper surface of the redistribution layer;
wherein the second-type chips are bonded to an upper surface of the TSV bridging substrates;
wherein the first molding compound layer is formed over the upper surface of the redistribution layer and encapsulates the first-type chips and the second-type chips;
wherein the plurality of PCB substrates are bonded to a lower surface of the redistribution layer;
wherein the plurality of third-type chips are bonded to a lower surface of the plurality of PCB substrates;
and
wherein the second molding compound layer is formed over the lower surface of the redistribution layer and encapsulates the plurality of third-type chips.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/165,157Filed 1 Jun 2023
Priority: CN 202310264780.X17 Mar 2023
Published: 3 Sep 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification28 codes

H10W 70/611
Insulating or insulated package substrates; Interposers; Redistribution layers: for connecting multiple chips together
H10W 90/401
Package configurations: characterised by multiple insulating or insulated package substrates, interposers or RDLs
H10W 40/03
Manufacture or treatment: of arrangements for cooling
H10W 40/235
Characterised by their places of attachment or cooling paths: attached to package parts