Integration scheme for fabricating high precision, low capacitor with unlanded via

Abstract

Semiconductor devices including a capacitor and methods of fabricating the semiconductor devices are disclosed. A semiconductor device includes an underlayer structure including a substrate onto which metal is patterned within a first dielectric material, wherein the patterned metal forms a first metal surface of the capacitor; a middle layer including a second dielectric material above the underlayer structure; an upper layer including a third dielectric material above the middle layer; and a supervia, formed though the upper layer and into the middle layer. The supervia is disposed in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor, and wherein a metal on the supervia forms a second metal surface of the capacitor above the first metal surface.

Dependencies are inferred from the claim text.