Anti-dishing structure for embedded memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu, Chih-Pin Huang
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Abstract
Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate including a logic region and a memory cell region. A logic device is arranged on the logic region. A memory device is arranged on the memory cell region. An isolation structure extends into a top surface of the semiconductor substrate, and laterally separates the logic region from the memory cell region. The isolation structure includes dielectric material and has an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.
Claims20
An integrated circuit (IC), comprising:
- a semiconductor substrate including a memory region and a logic region;
- an isolation structure disposed in the semiconductor substrate and separating the memory region from the logic region;
- and
- an array of split gate flash memory cell structures disposed on the memory region, the array of split gate flash memory cell structures comprising a central memory cell in a central region of the array and an edge memory cell in an edge region of the array, the edge region spaced between the central region and the isolation structure;
- wherein the edge memory cell includes an edge gate electrode and an edge gate electrode hardmask over the edge gate electrode, and the central memory cell includes a central gate electrode and a central gate electrode hardmask over the central gate electrode;
- wherein there is a difference in height as measured from a top surface of the semiconductor substrate between an upper surface of the edge gate electrode hardmask and an upper surface of the central gate electrode hardmask, the difference in height ranging between approximately 40 angstroms and approximately 10 angstroms.
An integrated circuit, comprising:
- a semiconductor substrate including a logic region and a memory cell region;
- an isolation structure extending into a top surface of the semiconductor substrate and separating the logic region from the memory cell region, the isolation structure comprising dielectric material;
- a logic device disposed on the logic region;
- a memory device disposed on the memory cell region, wherein the memory device includes a first select gate electrode;
- a dummy select gate structure made of conductive material disposed on the isolation structure, wherein an upper surface of the dummy select gate structure and an upper surface of the first select gate electrode have equal heights as measured from the top surface of the semiconductor substrate;
- a dielectric layer over the isolation structure, the dielectric layer comprising an uppermost surface and a recessed upper surface, the uppermost surface being level with the upper surface of the first select gate electrode and the recessed upper surface being below the uppermost surface;
- and
- an inter-layer dielectric (ILD) layer disposed over the recessed upper surface and having an upper surface that is level with the uppermost surface of the dielectric layer.
An integrated circuit (IC), comprising:
- a semiconductor substrate including a logic region and a memory cell region;
- a logic device on the logic region;
- a memory device on the memory cell region;
- and
- an isolation structure extending into a top surface of the semiconductor substrate and laterally separating the logic region from the memory cell region, the isolation structure comprising dielectric material and having an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.
Dependencies are inferred from the claim text.