Semiconductor Device And Method For Manufacturing The Semiconductor Device

A method for manufacturing a semiconductor device, comprising:

• forming a first conductive layer;
• forming a first insulating layer and a first conductive film over the first conductive layer;
• processing the first insulating layer and the first conductive film to form a second conductive layer from the first conductive film and to form a first opening reaching the first conductive layer in the first conductive film and the first insulating layer;
• processing the second conductive layer to form a third conductive layer;
• forming a first metal oxide film in contact with a top surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the third conductive layer in the first opening, and a top surface of the third conductive layer;
• processing the first metal oxide film to form a first semiconductor layer comprising a region overlapping with the first opening;
• forming a second insulating layer in contact with a top surface of the first semiconductor layer;
• forming a second conductive film over the second insulating layer;
• processing the second conductive film to form a fourth conductive layer comprising a region overlapping with the first semiconductor layer;
• forming a third insulating layer over the fourth conductive layer and the second insulating layer;
• forming a third conductive film over the third insulating layer;
• processing the third conductive film to form a fifth conductive layer comprising a region overlapping with the fourth conductive layer;
• forming a fourth insulating layer and a fourth conductive film over the fifth conductive layer and the third insulating layer;
• processing the fourth insulating layer and the fourth conductive film to form a sixth conductive layer from the fourth conductive film and to form, in the fourth conductive film and the fourth insulating layer, a second opening overlapping with a flat or substantially flat top surface of the fourth conductive layer so as to be apart from the fifth conductive layer in a plan view;
• processing the sixth conductive layer to form a seventh conductive layer;
• forming a second metal oxide film in contact with a top surface of the fourth conductive layer in the second opening, a side surface of the third insulating layer in the second opening, a side surface of the seventh conductive layer in the second opening, and a top surface of the seventh conductive layer;
• processing the second metal oxide film to form a second semiconductor layer comprising a region overlapping with the second opening;
• forming a fifth insulating layer in contact with a top surface of the second semiconductor layer;
• forming a fifth conductive film over the fifth insulating layer;
• and
• processing the fifth conductive film to form an eighth conductive layer comprising a region overlapping with the second semiconductor layer.

A method for manufacturing a semiconductor device, comprising:

• forming a first conductive layer;
• forming a first insulating layer and a first conductive film over the first conductive layer;
• processing the first insulating layer and the first conductive film to form a second conductive layer from the first conductive film and to form a first opening reaching the first conductive layer in the first conductive film and the first insulating layer;
• forming a first metal oxide film in contact with a top surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the second conductive layer in the first opening, and a top surface of the second conductive layer;
• processing the first metal oxide film to form a first semiconductor layer comprising a region overlapping with the first opening;
• processing the second conductive layer to form a third conductive layer comprising a region overlapping with the first semiconductor layer;
• forming a second insulating layer in contact with a top surface of the first semiconductor layer;
• forming a second conductive film over the second insulating layer;
• processing the second conductive film to form a fourth conductive layer comprising a region overlapping with the first semiconductor layer;
• forming a third insulating layer over the fourth conductive layer and the second insulating layer;
• forming a third conductive film over the third insulating layer;
• processing the third conductive film to form a fifth conductive layer comprising a region overlapping with the fourth conductive layer;
• forming a fourth insulating layer and a fourth conductive film over the fifth conductive layer and the third insulating layer;
• processing the fourth insulating layer and the fourth conductive film to form a sixth conductive layer from the fourth conductive film and to form, in the fourth conductive film and the fourth insulating layer, a second opening overlapping with a flat or substantially flat top surface of the fourth conductive layer so as to be apart from the fifth conductive layer in a plan view;
• forming a second metal oxide film in contact with a top surface of the fourth conductive layer in the second opening, a side surface of the third insulating layer in the second opening, a side surface of the fourth insulating layer in the second opening, a side surface of the sixth conductive layer in the second opening, and a top surface of the sixth conductive layer;
• processing the second metal oxide film to form a second semiconductor layer comprising a region overlapping with the second opening;
• processing the sixth conductive layer to form a seventh conductive layer comprising a region overlapping with the second semiconductor layer;
• forming a fifth insulating layer in contact with a top surface of the second semiconductor layer;
• forming a fifth conductive film over the fifth insulating layer;
• and
• processing the fifth conductive film to form an eighth conductive layer comprising a region overlapping with the second semiconductor layer.

A semiconductor device comprising:

• a memory portion and a processing portion,
• wherein the memory portion comprises a memory device and a sense amplifier,
• wherein the processing portion comprises a CPU, an MPU, or a GPU,
• wherein the sense amplifier and the processing portion are placed on a first layer,
• wherein the memory device is placed on a second layer and comprises a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer,
• wherein the second layer is stacked over the first layer,
• wherein the second transistor is provided over and overlapping with the first transistor,
• wherein the capacitor is provided over and overlapping with the first transistor,
• wherein a distance from a substrate to the source electrode of the first transistor and a distance from the substrate to the drain electrode of the first transistor are different from each other,
• wherein the first insulating layer is provided between the source electrode and the drain electrode of the first transistor and comprises a first opening reaching one of the source electrode and the drain electrode of the first transistor,
• wherein the other of the source electrode and the drain electrode of the first transistor is provided over the first insulating layer,
• wherein a semiconductor layer of the first transistor comprises a region in contact with a top surface of the one of the source electrode and the drain electrode of the first transistor in the first opening, a side surface of the first insulating layer in the first opening, and a top surface of the other of the source electrode and the drain electrode of the first transistor,
• wherein a gate insulating layer of the first transistor is provided over and in contact with the semiconductor layer of the first transistor,
• wherein a gate electrode of the first transistor is provided over the gate insulating layer of the first transistor to comprise a region overlapping with the semiconductor layer of the first transistor and is configured to serve as one of the source electrode and the drain electrode of the second transistor and as one electrode of the capacitor,
• wherein the second insulating layer is provided between the source electrode and the drain electrode of the second transistor and comprises a second opening reaching the gate electrode of the first transistor,
• wherein the second opening is positioned diagonally above the first opening,
• wherein the other of the source electrode and the drain electrode of the second transistor is provided over the second insulating layer,
• wherein a semiconductor layer of the second transistor comprises a region in contact with a top surface of the gate electrode of the first transistor in the second opening, a side surface of the second insulating layer in the second opening, and a top surface of the other of the source electrode and the drain electrode of the second transistor,
• wherein a gate insulating layer of the second transistor is provided over and in contact with the semiconductor layer of the second transistor,
• wherein a gate electrode of the second transistor is provided over the gate insulating layer of the second transistor so as to comprise a region overlapping with the semiconductor layer of the second transistor,
• wherein a dielectric layer of the capacitor is provided over the gate electrode of the first transistor, and
• wherein the other electrode of the capacitor comprises a region overlapping with the gate electrode of the first transistor and is provided over the dielectric layer of the capacitor and apart from the second opening in a plan view.