Methods and apparatus to generate clock signals using sampler-based phase detection

Phase locked loop (PLL) circuitry comprising:

• sampler circuitry having a first input to receive a reference clock signal (CLKM_REF), a second input to receive a feedback clock signal (CLKB_FBK), and an output;
• transconductor circuitry having an input coupled to the output of the sampler circuitry and having an output;
• auxiliary phase frequency detector (AUX PFD) circuitry having a first input to receive the reference clock signal, a second input to receive the feedback clock signal, and an output;
• reduced charge pump (RCP) circuitry having an input coupled to the AUX PFD circuitry and an output;
• filter circuitry having a first input coupled to the output of the transconductor circuitry, a second input coupled to the output of the RCP circuitry, and an output;
• and
• voltage controlled oscillator (VCO) circuitry having an input coupled to the output of the filter circuitry and having an output.

An apparatus comprising:

• extender circuitry including:
• a current source having a first terminal and a second terminal;
• a first transistor having a source terminal coupled to the current source, a control terminal coupled to the original reference clock signal, and a drain terminal;
• a first switch having a first terminal coupled to the drain terminal of the first transistor, a control terminal, and a second terminal;
• a first capacitor having a first terminal coupled to the second terminal of the first switch and a second terminal;
• a second transistor having a source terminal coupled to the drain terminal of the first transistor, a control terminal, and a drain terminal;
• a third transistor having a source terminal coupled to the current source, a control terminal coupled to the original reference clock signal, and a drain terminal;
• a second switch having a first terminal coupled to the drain terminal of the first transistor, a control terminal, and a second terminal;
• a second capacitor having a first terminal coupled to the second terminal of the second switch and a second terminal;
• a fourth transistor having a source terminal coupled to the drain terminal of the third transistor, a control terminal, and a drain;
• a resistor having a first terminal coupled to the drain terminal of the first transistor and a second terminal;
• a third switch having a first terminal coupled to the drain terminal of the first transistor, a control terminal, and a second terminal coupled to the drain terminal of the third transistor;
• a third capacitor having a first terminal coupled to the drain terminal of the second transistor and a second terminal coupled to the drain terminal of the first transistor;
• and
• common mode feedback (CMFB) circuitry having a first terminal coupled to the drain terminal of the first transistor, a second terminal coupled to the drain terminal of the third transistor, and a third terminal coupled to the drain terminals of both the third and fourth transistors;
• and
• switch capacitor filter circuitry including:
• a first capacitor having a first terminal coupled to the second terminal of the first switch and a second terminal;
• a second switch having a first terminal coupled to the second terminal of the first capacitor, a control terminal and a second terminal;
• a third switch having a first terminal coupled to the second terminal of the first capacitor, a control terminal, and a second terminal;
• a fourth switch having a first terminal coupled to the second terminal of the first switch, a control terminal and a second terminal coupled to an output of transconductor circuitry;
• a second capacitor having a first terminal coupled to the second terminal of the first switch and a second terminal;
• and
• a third capacitor having a first terminal coupled to the second terminal of the fourth switch and a second terminal.