Dynamic control of resistive random-access memory

A computer program product embodied in a non-transitory computer readable medium for memory control, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing a resistive random-access memory (ReRAM) memory cell array;
• generating a variable pulse width primeval signal, wherein the variable pulse width primeval signal is generated using a pulse width modulator, wherein the variable pulse width primeval signal is generated at an initial voltage, and wherein a width of the variable pulse width primeval signal determines a duration of a variable pulse width programming signal;
• adjusting the initial voltage of the variable pulse width primeval signal, wherein the initial voltage is adjusted based on a binary digital input and a ReRAM memory cell array supply voltage, and wherein the adjusting determines an output voltage of the variable pulse width programming signal;
• routing the variable pulse width programming signal to a portion of the ReRAM memory cell array, based on a ReRAM operation;
• and
• programming the portion of the ReRAM memory cell array, using the variable pulse width programming signal that was routed.

An apparatus for memory operation control comprising:

• a resistive random-access memory (ReRAM) memory cell array, wherein the ReRAM array comprises wordlines, bitlines, and select lines;
• a first control logic coupled to the wordlines of the ReRAM array, wherein the first control logic drives the wordlines of the ReRAM array, based on a first selection input;
• a second control logic coupled to the bitlines of the ReRAM array, wherein the second control logic drives the bitlines of the ReRAM array, based on a second selection input;
• a third control logic coupled to the select lines of the ReRAM array, wherein the third control logic drives the select lines of the ReRAM array, based on a third selection input;
• and
• input decoding logic coupled to the first control logic, the second control logic, and the third control logic, wherein the input decoding logic enables ReRAM operation selection, and wherein an operation that was selected is performed with a variable pulse width, adjusted voltage programming signal.