High signal-to-noise-ratio memory cell programming for in-memory computing
AssigneeOmniVision Technologies, Inc.
InventorDaisuke Saito
Life of this patent
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Abstract
An in-memory computing system includes a cross-bar array of memory cells, each having a cell transistor and a memristor connected in series between a select line and a bit line. A group of programming transistors, located outside the cross-bar array and fewer in number than the memory cells, is selectively connected in parallel with cell transistors of a common row during a write mode and isolated during a read mode. This configuration increases programming current without enlarging a footprint of the cross-bar array, enabling multi-level conductance states and improved signal-to-noise ratio for analog in-memory computing. In some embodiments, the in-memory computing system is integrated with an image sensor die for on-sensor inference.
Claims20
An in-memory computing system with high signal-to-noise-ratio memory cell programming, comprising:
- a computational block formed with a cross-bar array of memory cells, wherein each memory cell includes a cell transistor and a memristor connected in series between a select line (SL) and a bit line (BL);
- and
- a group of programming transistors located outside a main body of the cross-bar array and fewer in number than the memory cells, wherein each programming transistor is selectively connected in parallel with a plurality of cell transistors of a common row during a write mode of the memory cell and is isolated from the cell transistors when the memory cells are not in the write mode.
A method for high signal-to-noise-ratio programming of memory cell for in-memory computing, comprising:
- fabricating a 1T1R array of memory cells that each include one cell transistor and one memristor connected in series between a bit line (BL) and a select line (SL);
- fabricating a group of programming transistors external to the 1T1R array, wherein each of the programming transistors is electrically coupled in parallel with at least one different one of the cell transistors;
- fabricating, for each programming transistor, an isolating switch coupled in series with the programming transistor;
- and
- controlling each of the programming transistors to provide at least part of a programming current for at least one of the memristors during a write mode of the memristor and controlling the corresponding isolating switch to electrically disconnect the programming transistor from the memory cells when not during the write mode.
Dependencies are inferred from the claim text.