Semiconductor structures in memory devices

A memory device, comprising:

• a first semiconductor structure comprising a memory array comprising a plurality of memory banks;
• and
• a second semiconductor structure stacked with the first semiconductor structure, wherein the second semiconductor structure comprises a control circuitry comprising:
• a plurality of bank circuits corresponding to the plurality of memory banks;
• and
• a peripheral circuit arranged to one side of the plurality of bank circuits,
• wherein the peripheral circuit comprises a first regulator coupled to bit lines in a first memory bank of the plurality of memory banks, and
• wherein a first bank circuit corresponding to the first memory bank comprises a second regulator, wherein the second regulator is coupled to the bit lines in the first memory bank.

A memory system, comprising:

• a memory device comprising:
• a memory array comprising a plurality of memory banks;
• and
• a control circuitry comprising:
• a first regulator coupled to bit lines in a first memory bank of the plurality of memory banks;
• and
• a second regulator coupled to the bit lines in the first memory bank, wherein an output of the first regulator is coupled to an output of the second regulator;
• and
• a memory controller coupled to the memory device and configured to control the memory device.