Vector unit with an activation function accelerator pipeline

A computer program product embodied in a non-transitory computer readable medium for matrix processing, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing a processor core, wherein the processor core executes an instruction set architecture (ISA), wherein the processor core includes a vector unit, wherein the vector unit includes one or more execution pipelines, and wherein the processor core calculates one or more activation functions associated with a machine learning model;
• extending the ISA, wherein the extending includes a custom vector instruction, wherein the custom vector instruction is based on a core activation function, and wherein a first activation function within the one or more activation functions is based on the core activation function;
• implementing, in the vector unit, the custom vector instruction, wherein the implementing is based on a plurality of combinational logic cones, wherein the plurality of combinational logic cones calculates a plurality of output bits associated with a result of the core activation function;
• and
• computing, by the processor core, the first activation function, wherein the computing is based on the custom vector instruction, and wherein the custom vector instruction accesses, within the vector unit, the plurality of combinational logic cones.

A computer system for matrix processing comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a processor core, wherein the processor core executes an instruction set architecture (ISA), wherein the processor core includes a vector unit, wherein the vector unit includes one or more execution pipelines, and wherein the processor core calculates one or more activation functions associated with a machine learning model;
• extend the ISA, wherein the extending includes a custom vector instruction, wherein the custom vector instruction is based on a core activation function, and wherein a first activation function within the one or more activation functions is based on the core activation function;
• implement, in the vector unit, the custom vector instruction, wherein the implementing is based on a plurality of combinational logic cones, wherein the plurality of combinational logic cones calculates a plurality of output bits associated with a result of the core activation function;
• and
• compute, by the processor core, the first activation function, wherein the computing is based on the custom vector instruction, and wherein the custom vector instruction accesses, within the vector unit, the plurality of combinational logic cones.