Tracking crc (cyclic redundancy check) errors per memory write transaction
AssigneeIntel Products IP LLC
InventorsChristopher P. MOZAK, James A. McCALL
Life of this patent
Estimating the term…
Abstract
A memory device includes CRC (cyclic redundance check) circuitry to detect CRC errors in write transactions. The CRC circuitry computes CRC for a data block to compare with CRC bits that were computed and sent by the memory controller. The memory device records the pass/fail status of write transactions in an error status register readable by the memory controller. The memory device can trigger the ALERT_n signal in response to an error.
Claims18
A computing device comprising:
- circuitry coupled to a memory, the circuitry to:
- compute error detecting data bits on a data block associated with a write transaction;
- and
- store the computed error detecting data bits in the memory, wherein the data bits are communicated over a multi-unit interval burst length, wherein the burst length is dynamically configurable.
A memory device comprising:
- on-memory error detection code circuitry to:
- compute error detecting data bits on a data block associated with a write transaction;
- and
- store the computed error detecting data bits in a memory associated with the memory device, wherein the data bits are communicated over a multi-unit interval burst length, wherein the burst length is dynamically configurable.
At least one computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:
- computing, by circuitry of the computing device, error detecting data bits on a data block associated with a write transaction;
- and
- storing the computed error detecting data bits in a memory, wherein the data bits are communicated over a multi-unit interval burst length, wherein the burst length is dynamically configurable.
Dependencies are inferred from the claim text.