Semiconductor substrate having a hybrid alignment structure
AssigneeInfineon Technologies AG
InventorJoerg Ortner
Life of this patent
Estimating the term…
Abstract
A semiconductor substrate includes an alignment mark and a base layer. The base layer includes a first sub-structure of the alignment mark and a second sub-structure of the alignment mark. The first sub-structure is formed by a first mask-and-exposure lithography process and the second sub-structure is formed by a second mask-and-exposure lithography process. The semiconductor substrate further includes a structured layer disposed over the base layer. The first sub-structure and the second sub-structure are configured to provide alignment information for alignment of the structured layer.
Claims25
A semiconductor substrate, comprising:
- an alignment mark;
- a base layer, the base layer comprising a first sub-structure of the alignment mark and a second sub-structure of the alignment mark, the first sub-structure being formed by a first mask-and-exposure lithography process and the second sub-structure being formed by a second mask-and-exposure lithography process;
- and
- a structured layer disposed over the base layer,
- wherein the first sub-structure and the second sub-structure are configured to provide alignment information for alignment of the structured layer.
A method of manufacturing a semiconductor substrate comprising an alignment mark, the method comprising:
- forming a first sub-structure of the alignment mark in a base layer of the semiconductor substrate by a first mask-and-exposure lithography process;
- forming a second sub-structure of the alignment mark in the base layer by a second mask-and-exposure lithography process;
- forming a layer over the base layer;
- and
- structuring the layer based on alignment information from the first sub-structure and alignment information from the second sub-structure.
A semiconductor substrate, comprising:
- a primary overlay measurement mark;
- a secondary overlay measurement mark;
- a base layer, the base layer comprising a first sub-structure of the primary overlay measurement mark and a second sub-structure of the primary overlay measurement mark, the first sub-structure being formed by a first mask-and-exposure lithography process and the second sub-structure being formed by a second mask-and-exposure lithography process;
- and
- a structured layer disposed over the base layer, the structured layer comprising the secondary overlay measurement mark.
A method of performing an overlay error measurement on a semiconductor substrate comprising a primary overlay measurement mark and a secondary overlay measurement mark, the method comprising:
- forming a first sub-structure of the primary overlay measurement mark in a base layer of the semiconductor substrate by a first mask-and-exposure lithography process;
- forming a second sub-structure of the primary overlay measurement mark in the base layer by a second mask-and-exposure lithography process;
- forming a layer over the base layer, the layer comprising the secondary overlay measurement mark;
- optically recognizing the primary overlay measurement mark and the secondary overlay measurement mark to provide a first signal based on the contrast of the primary overlay measurement mark and a second signal based on the contrast of the secondary overlay measurement mark;
- and
- evaluating the first signal and the second signal to obtain a set of overlay error parameters.
Dependencies are inferred from the claim text.