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US 2026/0259259 A1Published application
Common debug network for chiplet and multi-chipset architectures
AssigneeQUALCOMM Incorporated
InventorsManas Ranjan MOHANTA, Sakthikumaran SAMIAPPA
Life of this patent
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Abstract
A common debug network is provided for a chiplet-based or a chipset-based system. In the systems, a primary die includes an external debugger interface for coupling to an external debugger. The external debugger may debug a target circuit in the primary die through the external debugger interface. Alternatively, the external debugger may debug a target circuit in a secondary die through a common debug network coupled between the primary die and the secondary die.
Claims21
A system, comprising:
- a first chiplet die including:
- a first debugging interface for coupling to an external debugger;
- a first multiplexer coupled to the first debugging interface;
- a first target circuit;
- a first debug subsystem configured to debug the first target circuit with first debugging signals coupled through the first multiplexer from the first debugging interface;
- a first set of terminals from a first inter-chiplet interface, wherein the first set of terminals is coupled to the first multiplexer;
- and
- a second chiplet die including:
- a second set of terminals from a second inter-chiplet interface, wherein the second set of terminals is coupled to the first set of terminals;
- a second multiplexer coupled to the second set of terminals;
- a second target circuit;
- and
- a second debug subsystem configured to debug the second target circuit with second debugging signals coupled through the second multiplexer from the second set of terminals.
10 more elements
A method of debugging, comprising:
- coupling a plurality of first debugging signals from an external debugger through a first multiplexer in a first die to a first debug subsystem in the first die;
- debugging a first target circuit in the first die using the plurality of first debugging signals and the first debug subsystem;
- coupling a plurality of second debugging signals from the external debugger through the first multiplexer and through a second multiplexer in a second die to a second debug subsystem in the second die;
- and
- debugging a second target circuit in the second die using the plurality of second debugging signals and the second debug subsystem.
2 more elements
A system, comprising:
- a first chipset die including:
- a first debugging interface for coupling to an external debugger;
- a first multiplexer coupled to the first debugging interface;
- a first target circuit;
- a first debug subsystem configured to debug the first target circuit with first debugging signals coupled through the first multiplexer from the first debugging interface;
- a first set of terminals from a first die-to-die interface, wherein the first set of terminals is coupled to the first multiplexer;
- and
- a second chiplet die including:
- a second set of terminals from a second die-to-die interface, wherein the second set of terminals is coupled to the first set of terminals;
- a second multiplexer coupled to the second set of terminals;
- a second target circuit;
- and
- a second debug subsystem configured to debug the second target circuit with second debugging signals coupled through the second multiplexer from the second set of terminals.
10 more elements
Dependencies are inferred from the claim text.