Analog circuit having reconfiguration means for a stress test and/or for an iddq test, and associated methods

An analog circuit based on MOS, BiCMOS, or CMOS;

• wherein the analog circuit is designed to fulfill a predetermined circuit purpose in a normal state of the analog circuit,
• wherein the analog circuit has one or more input signals and/or one or more output signals,
• wherein the analog circuit has at least one analog signal within the analog circuit
• wherein the analog circuit is coupled to a test logic,
• wherein the test logic is designed to set the analog circuit to the normal state and at least a first test state,
• wherein the analog circuit comprises first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30),
• wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are designed to perform a function of the analog circuit in accordance with the predetermined circuit purpose of the analog circuit in the normal state of the analog circuit,
• wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) each have a control electrode,
• wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are designed to also be operated as switches by their respective control electrodes,
• wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in a respective operation as switches each have an on state and an off state as respective switching states,
• wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are fully switched on in the on state,
• wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are fully switched off in the off state,
• wherein the analog circuit comprises second components (S1 to S9;
• G1 to G9),
• wherein the test logic is designed to use the second components (S1 to S9;
• G1 to G9) in the first test state of the analog circuit to set the switching states of at least one first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30),
• wherein the control electrode (33, 34, 36, 37) of the at least one first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is not directly connected to an input signal or not directly connected to an output signal,
• wherein the test logic is designed to switch this control electrode (33, 34, 36, 37) of the at least one first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in the first test state from the rest of the analog circuit by use of at least one switch (S1, S2, S3, S4),
• wherein the test logic is designed to connect the control electrodes (33, 34, 36, 37) of the at least one first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) from the rest of the analog circuit by use of the at least the switch (S1, S2, S3, S4) in the normal state,
• wherein the test logic is designed to connect, in the first test state, this control electrode (33, 34, 36, 37, 39) of the at least one first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) by use of at least one first means (G1, G2, G5, G6) in an on state or to switch them off in an off state, and
• wherein the test logic is designed to control the at least one first means (G1, G2, G5, G6) in the normal state such that the at least one first means (G1, G2, G5, G6) switches the control electrode (33, 34, 36, 37, 39) of the at least one first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in the normal state of the analog circuit.