Interposer, semiconductor package including interposer, and testing method for interposer
AssigneeSamsung Electronics Co., Ltd.
InventorsSeungwon BAEK, Minkyu KIM, Joongsun KIM, Pyunghwa HAN, Kyuil HWANG
Life of this patent
Estimating the term…
Abstract
Provided are an interposer capable of early testing for defects without using an intermediate medium, a semiconductor package including the interposer, and a testing method for the interposer. The interposer includes a body layer, a wiring layer disposed on the body layer, a through post penetrating through the body layer, an interposer pad disposed on the wiring layer, and a test pad disposed on a connection area of the wiring layer and connected to a part of the interposer pad.
Claims20
An interposer comprising:
- a body layer;
- a wiring layer disposed on the body layer;
- a through post penetrating through the body layer;
- an interposer pad disposed on the wiring layer;
- and
- a test pad disposed on a connection area of the wiring layer and connected to a portion of the interposer pad.
A semiconductor package comprising:
- a package substrate;
- an interposer on the package substrate;
- at least one first semiconductor device arranged in a central portion on an upper surface of the interposer in a first direction;
- and
- second semiconductor devices disposed on the upper surface of the interposer on both sides of the at least one first semiconductor device in the first direction,
- wherein the interposer comprises a body layer, a wiring layer disposed on the body layer, a through post penetrating through the body layer, an interposer pad disposed on the wiring layer, and a test pad disposed on a connection area of the wiring layer and connected to a portion of the interposer pad.
A semiconductor package comprising:
- a package substrate;
- an interposer on the package substrate;
- at least one logic device arranged in a central portion of an upper surface of the interposer in a first direction;
- and
- a high bandwidth memory (HBM) package disposed on the upper surface of the interposer on both sides of the at least one logic device in the first direction,
- wherein the interposer comprises a body layer, a wiring layer disposed on the body layer, a silicon (Si)-bridge arranged in the body layer and the wiring layer, a through post penetrating through the body layer, an interposer pad disposed on the wiring layer and the Si-bridge, and a test pad disposed on the Si-bridge and connected to a portion of the interposer pad.
Dependencies are inferred from the claim text.