Semiconductor structure with reduced gate contact resistance and method for manufacturing the same

A method for manufacturing a semiconductor structure, comprising:

• forming a base structure on a substrate, the base structure including a gate electrode and a gate dielectric layer covering the gate electrode;
• forming a via opening extending from an upper surface of the base structure to expose a surface region of the gate dielectric layer;
• performing a non-plasma etching process on the surface region of the gate dielectric layer through the via opening until the via opening penetrates the gate dielectric layer to expose a portion of the gate electrode, the non-plasma etching process including
• subjecting the surface region of the gate dielectric layer to react with a first halogen-containing gas so as to form a first film, the first halogen-containing gas containing a first halogen,
• performing an atomic layer clean treatment which includes
• subjecting the first film to react with a second halogen-containing gas, so as to remove the first film and to form a second film different from the first film, the second halogen-containing gas containing a second halogen different from the first halogen, and
• subjecting the second film to react with the first halogen-containing gas, so as to remove the second film and to form the first film, and
• repeating the atomic layer clean treatment until the portion of the gate electrode is exposed through the via opening;
• and
• forming a conductive cap portion on the portion of the gate electrode, so as to prevent the portion of the gate electrode from being exposed through the via opening,
• the non-plasma etching process and formation of the conductive cap portion being performed without breaking vacuum.

A method for manufacturing a semiconductor structure, comprising:

• forming a base structure on a substrate, the base structure including
• channel portions which are vertically stacked and spaced apart from each other,
• a protection portion which is disposed on and spaced apart from an uppermost one of the channel portions,
• a gate dielectric layer which includes a first dielectric portion disposed beneath the protection portion and a second dielectric portion disposed around the channel portions, and
• a gate electrode disposed on the gate dielectric layer to fill spaces each of which is located between two corresponding adjacent ones of the channel portions and the protection portion;
• forming a via opening which penetrates the protection portion to terminate at the first dielectric portion;
• performing a non-plasma etching process on the first dielectric portion through the via opening until the via opening penetrates the first dielectric portion to expose a portion of the gate electrode;
• and
• forming a conductive cap portion on the portion of the gate electrode, so as to prevent the portion of the gate electrode from being exposed through the via opening,
• the non-plasma etching process and formation of the conductive cap portion being performed without breaking vacuum.