# US 2026/0255667 A1 · Semiconductor device

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- Number: US 2026/0255667 A1
- Document ID: US20260255667A1
- Status: Published application
- Kind: A1
- Application number: 19/653,079
- Filed: 2026-04-20
- Published: 2026-08-27
- Earliest claimed: 2021-12-20
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chih-Kai Hsu; Ssu-I Fu; Yu-Hsiang Lin; Chien-Ting Lin
- Web page: https://patentgrep.com/patent/US20260255667A1

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/027: {by etching at gate locations}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 64/514: {characterised by the insulating layers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs}
- H10D 89/931: {characterised by the dispositions of the protective arrangements}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate, a first transistor, a second transistor and a third transistor. The substrate includes a high-voltage (HV) area, a medium-voltage (MV) area, and a low-voltage (LV) area. The first transistor is disposed in the HV area and includes a first gate dielectric layer and a first gate electrode. The second transistor is disposed in the LV area and includes a plurality of fin-shaped structures and a second gate electrode. The third transistor is disposed in the MV area and includes a third gate dielectric layer and a third gate electrode. The topmost surfaces of the first gate electrode, the second gate electrode and the third gate electrode are coplanar with each other.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate, comprising a high-voltage area, a medium-voltage area, and a low-voltage area;
two first doped regions, disposed in the substrate and within the high-voltage area, the two first doped regions being parallel extended in a first direction;
a first gate electrode, disposed on the substrate and within the high-voltage area, the first gate electrode extending in the first direction and appearing between the two first doped regions,
a second doped region, disposed in the substrate and within the medium-voltage area, the second doped region extending in the first direction;
a second gate electrode, disposed on the substrate and within the medium-voltage area, the second gate electrode extending in the first direction and partially overlaying the second doped region;
a plurality of fin-shaped structures, disposed in the substrate and within the low-voltage area, the plurality of fin-shaped structures being parallel extended in the first direction;
a third gate electrode, disposed on the substrate and within the low-voltage area, the third gate electrode extending in a second direction that is perpendicular to the first direction, across the plurality of fin-shaped structures; and
a shallow trench isolation structure, disposed in the substrate and surrounding the two first doped regions, the second doped region, and the plurality of fin-shaped structures, respectively;
wherein the first gate electrode, the second gate electrode, each of the two first doped regions, and the second doped region each comprises a long side extending in the first direction and a short side extending in the second direction, the third gate electrode comprises a long side extending in the second direction and a short side extending in the first direction, and the long side of the first gate electrode is the same as the long side of the second gate electrode, and is greater than the long side of the third gate electrode.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a protective structure, disposed in the substrate and surrounding surround the high-voltage area, wherein the protective structure comprises a first portion extending in the first direction and a second portion extending in the second direction, and the first portion of the protective structure is disposed between one of the two first doped regions and the second doped region.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the shallow trench isolation structure is partially disposed in the two first doped regions.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a plurality of third doped regions, disposed in the plurality of fin-shaped structures, at two opposite sides of the third gate electrode.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the long side of the first gate electrode is greater than the long side of each of the two first doped region, and the long side of each of the two first doped region is greater than the long side of the third gate electrode.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the long side of each of the two first doped region is the same as the long side of the second doped region.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising a first gate dielectric layer disposed below the first gate electrode, wherein the first gate dielectric layer comprises a long side extending in the first direction and a short side extending in the second direction, and the long side of the first gate dielectric layer is shorter than the long side of the first gate electrode.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the short side is shorter than the long side of each of the two first doped regions.

### Claim 9

A semiconductor device, comprising:
a substrate, comprising a high-voltage area, a medium-voltage area, and a low-voltage area;
a plurality of shallow trench isolation structures, disposed in the substrate and located in the high-voltage area, the medium-voltage area and the low-voltage area, respectively;
a first transistor, disposed in the high-voltage area, wherein the first transistor comprises:
a first gate dielectric layer, disposed on a first plane of the substrate, wherein a portion of the first gate dielectric layer protrudes from a top surface of the plurality of shallow trench isolation structures; and
a first gate electrode, disposed on the first gate dielectric layer;
a second transistor, disposed in the low-voltage area, wherein the second transistor comprises:
a plurality of fin-shaped structures, protruding from a second plane of the substrate; and
a second gate electrode, crossing the plurality of fin-shaped structures; and
a third transistor, disposed in the medium-voltage area, wherein the third transistor comprises:
a third gate dielectric layer, disposed on a third plane of the substrate; and
a third gate electrode, disposed on the third gate dielectric layer, wherein a topmost surface of the first gate electrode, a topmost surface of the second gate electrode, and a topmost surface of the third gate electrode are coplanar with each other.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein a top surface of the first gate dielectric layer is coplanar with the topmost surface of the plurality of fin-shaped structures.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the first gate electrode has an inverted U-shape and wraps around the portion of the first gate dielectric layer.