Multi-threshold voltage integration scheme for semiconductor devices

An electronic device comprising:

• a P-dipole stack and an N-dipole stack on a substrate comprising silicon (Si) or silicon oxide (SiOx), each of the P-dipole stack and the N-dipole stack on a top surface of a channel located between a source and a drain on the substrate, each of the P-dipole stack and the N-dipole stack comprising:
• an interfacial layer comprising silicon oxide (SiOx) on the top surface of the channel;
• a hafnium-containing layer on the interfacial layer, the hafnium-containing layer having a thickness of less than or equal to 5 Å;
• a dipole layer on the hafnium-containing layer, the dipole layer on the N-dipole stack having a first thickness and the dipole layer on the P-dipole stack having a second thickness;
• and
• a high-κ dielectric layer having a thickness in a range of from 10 Å to 20 Å on the dipole layer, the high-κ dielectric layer comprising one or more of hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx).