Transistor with active area under gate runner

A silicon carbide transistor, comprising:

• a gate runner coupled to a gate of the silicon carbide transistor;
• a source region formed in an silicon carbide substrate;
• and
• a silicide layer coupling a source metal to the source region, wherein the silicide layer comprises:
• a silicide contact area located under the source metal and coupling the source metal to a first portion of the source region under the source metal;
• and
• a silicide extension area located under an insulator and providing a lateral coupling from the source metal to a second portion of the source region located under the insulator, wherein the silicide extension area extends laterally under the gate runner, wherein the silicide extension area extends laterally under the gate runner.

A transistor, comprising:

• a source region;
• a silicide layer coupling a source metal to the source region, wherein the silicide layer comprises:
• a silicide contact area located under the source metal and coupling the source metal to a first portion of the source region under the source metal;
• and
• a silicide extension area located under an insulator and providing a lateral coupling from the source metal to a second portion of the source region located under the insulator;
• and
• a gate runner coupled to a gate of the transistor, the gate runner disposed along an axis orthogonal to a linear layout of a plurality of active cells of the transistor, wherein the active cells of the transistor extend under the gate runner.