Low temperature n-type contact epi formation

A method of forming a logic device, the method comprising:

• non-selectively depositing an amorphous silicon layer on a top surface of a first dielectric material and a sidewall surface of a second dielectric material of at least one contact trench on a substrate and a crystalline silicon layer on a bottom surface of the at least one contact trench at a first temperature less than or equal to 400 °C, the bottom surface including a source/drain material comprising a metal layer on a metal silicide layer on a doped silicon layer on the substrate;
• and
• selectively removing the amorphous silicon layer from the top surface and the sidewall surface at a second temperature is in a range of from 0 °C to 20 °C,
• wherein the method is performed in a processing chamber without breaking vacuum.

A processing tool comprising:

• a pre-clean chamber having a substrate support therein;
• a non-selective silicon deposition chamber;
• a selective etching chamber;
• a robot configured to access the pre-clean chamber, the non-selective silicon deposition chamber, and the selective etching chamber;
• and
• a controller connected to the pre-clean chamber, the non-selective silicon deposition chamber, and the selective etching chamber, the controller having one or more configurations selected from:
• cleaning a substrate, non-selectively forming an amorphous silicon layer and a crystalline silicon layer, and selectively etching the substrate,
• wherein the non-selective silicon deposition chamber and the selective etching chamber are continuously kept under vacuum.