US 2026/0255633 A1Published application

Semiconductor device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsYoshiyuki KUROKAWA, Yuto YAKUBO, Kazuma FURUTANI, Kouhei TOYOTAKA

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Abstract

A semiconductor device with a novel structure is provided. The semiconductor device includes a first arithmetic device including a register, a second arithmetic device including memory circuits, layer selection circuits, and an arithmetic circuit. The first arithmetic device and the second arithmetic device are each provided in an element layer where a plurality of second element layers are stacked over a first element layer. The register includes flip-flop and data retention circuits. The flip-flop and the arithmetic circuit are provided in the first element layer. The data retention circuits are provided in the plurality of second element layers over the first element layer provided with the flip-flop. The memory circuits and the layer selection circuit are provided in the plurality of second element layers over the first element layer provided with the arithmetic circuit.

Claims8

Dependent claims

A semiconductor device comprising a first arithmetic device comprising a register and a second arithmetic device comprising a plurality of memory circuits, a plurality of layer selection circuits, and an arithmetic circuit,

wherein the first arithmetic device and the second arithmetic device are provided in an element layer in which a plurality of second element layers are stacked over a first element layer, wherein the first element layer comprises a first transistor comprising silicon in a first semiconductor layer comprising a first channel formation region, wherein the second element layer comprises a second transistor comprising an oxide semiconductor in a second semiconductor layer comprising a second channel formation region, wherein the register comprises a flip-flop and a plurality of data retention circuits, wherein the flip-flop and the arithmetic circuit are provided in the first element layer, wherein the data retention circuit is provided in the of second element layer over the flip-flop and
wherein the memory circuit and the layer selection circuit are provided in the second element layer over the arithmetic circuit-provided

Dependencies are inferred from the claim text.