Horizontal memory structures in logic devices and methods of manufacturing the same

A circuit device, comprising:

• a semiconductor substrate comprising a first transistor structure in a memory region of the semiconductor substrate and a second transistor structure in a logic region of the semiconductor substrate adjacent the memory region, wherein:
• the first transistor structure comprises at least one first channel region extending between first source/drain regions having first source/drain contacts thereon, respectively, and a first spacer that electrically isolates one of the first source/drain regions from one of the first source/drain contacts thereon;
• and
• the second transistor structure comprises at least one second channel region extending between second source/drain regions having second source/drain contacts directly thereon, respectively.

A method of fabricating a circuit device, the method comprising:

• providing a semiconductor substrate having a memory region and a logic region;
• forming first source/drain regions with at least one first channel region therebetween in the memory region and second source/drain regions with at least one second channel region therebetween in the logic region;
• forming a dielectric material on the memory region and the logic region of the semiconductor substrate;
• and
• forming first and second source/drain contacts on the first and second source/drain regions, respectively,
• wherein the dielectric material on the memory region provides first spacers that electrically isolate the first source/drain regions from the first source/drain contacts thereon.