Method of manufacturing multilayer pcb for semiconductor testing and multilayer pcb manufactured thereby

A method of manufacturing a multilayer printed circuit board (PCB) for semiconductor testing, comprising:

• an operation (h) of preparing a copper clad laminate (CCL) plate in which copper foil layers serving as dummy layers are formed on both surfaces of a core layer;
• an operation (i) of processing a plated through hole (PTH) in the CCL plate;
• an operation (j) of forming a plurality of fine pads around the PTH;
• an operation (k) of, in a state in which copper foils are laminated on upper and lower layers of the CCL plate with prepreg interposed therebetween, etching the copper foils to reduce a thickness thereof and then forming the PTH and a fine hole;
• an operation (l) of forming chemical copper on the copper foils of an intermediate product subjected to the operation (k);
• an operation (m) of forming electrolytic copper in a state in which a photo resist image is formed using a dry film and forming the PTH and a fine pillar during the forming of the electrolytic copper;
• an operation (n) of forming a circuit pattern by removing the chemical copper and the remaining portions of the copper foils by etching after stripping the dry film;
• and
• an operation (o) of repeatedly performing the operations (k) to (n) until all layers are completely formed.