Synchronization architecture for inter-chiplet communication within three-dimensional integrated circuit

A receiver device, comprising:

• a deserializer, configured to convert an input serial data signal into a parallel data signal using a predetermined demultiplexing ratio, wherein the input serial data signal is with reference to an input clock signal and a valid signal received from a transmitter device;
• and
• a dynamic reset generation circuit, configured to, in response to assertion of the valid signal, de-assert a reset signal for use by the deserializer at a rising edge of a first clock signal subsequent to the assertion of the valid signal,
• wherein a frequency of the first clock signal is substantially equal to that of the input clock signal.

A method, comprising:

• converting an input serial data signal to a first partial serial data signal and a second partial serial data signal using a first clock signal set;
• demultiplexing the first partial serial data signal and the second partial serial data signal to generate a first half parallel data signal and a second half parallel data signal using a second clock signal set, respectively;
• and
• de-asserting a reset signal of a clock divider in response to a valid frame received from a transmitter device and a first clock signal within the first clock signal set.