Systems and methods for common-mode rejection in signal processing systems

An apparatus comprising:

• a first input terminal configured to receive a first input signal;
• a second input terminal configured to receive a second input signal;
• a first converter coupled to the first input terminal and configured to generate a first signal based on the first input signal;
• a second converter coupled to the second input terminal and configured to generate a second signal based on the second input signal;
• and
• a first circuit coupled to the first converter and the second converter, the first circuit being configured to:
• generate a third signal by adjusting the first signal based on a gain mismatch between the first converter and the second converter;
• generate a fourth signal by adjusting the second signal based on the gain mismatch;
• and
• generate an output signal based at least on the third signal and the fourth signal.

An apparatus comprising:

• a first input terminal configured to receive a first input signal;
• a second input terminal configured to receive a second input signal;
• a first converter coupled to the first input terminal and configured to generate a first signal based on the first input signal;
• a second converter coupled to the second input terminal and configured to generate a second signal based on the second input signal;
• and
• a first circuit coupled to the first converter and the second converter, the first circuit being configured to:
• determine a gain mismatch between the first converter and the second converter based at least on the first signal and the second signal;
• generate a third signal by adjusting the first signal based on the gain mismatch;
• generate a fourth signal by adjusting the second signal based on the gain mismatch;
• and
• generate an output signal based at least on the third signal and the fourth signal.