Phase-locked circuit, imaging device, and electronic circuit
AssigneeSony Semiconductor Solutions Corporation
InventorKeigo Bunsen
Life of this patent
Estimating the term…
Abstract
To make it possible to reduce jitter while suppressing an increase in circuit size of a phase-locked circuit. A phase-locked circuit includes a sample hold circuit configured to sub-sample an input signal, on the basis of a reference signal, a voltage-to-time converter configured to convert a voltage of the input signal sub-sampled by the sample hold circuit into a time difference, and a time-to-digital converter configured to detect the time difference converted by the voltage-to-time converter. The sample hold circuit, the voltage-to-time converter, and the time-to-digital converter may constitute a time domain ADC. The phase-locked circuit may further include a digitally-controlled oscillator configured to generate the input signal.
Claims13
A phase-locked circuit comprising:
- a sample hold circuit configured to sub-sample an input signal, on the basis of a reference signal;
- a voltage-to-time converter configured to convert a voltage of the input signal sub-sampled by the sample hold circuit into a time difference;
- and
- a time-to-digital converter configured to detect the time difference converted by the voltage-to-time converter.
An imaging device comprising:
- an imaging section including a plurality of pixels;
- and
- a phase-locked circuit configured to generate a clock signal for setting an operation timing of the imaging section, wherein
- the phase-locked circuit includes
- a sample hold circuit configured to sub-sample the clock signal, on the basis of a reference clock,
- a voltage-to-time converter configured to convert a voltage of the clock signal sub-sampled by the sample hold circuit into a time difference, and
- a time-to-digital converter configured to detect the time difference converted by the voltage-to-time converter.
An electronic circuit comprising:
- a circuit unit configured to operate on the basis of a clock signal;
- and
- a phase-locked circuit configured to generate a clock signal for setting an operation timing of the circuit unit, wherein
- the phase-locked circuit includes
- a sample hold circuit configured to sub-sample the clock signal, on the basis of a reference clock,
- a voltage-to-time converter configured to convert a voltage of the clock signal sub-sampled by the sample hold circuit into a time difference, and
- a time-to-digital converter configured to detect the time difference converted by the voltage-to-time converter.
Dependencies are inferred from the claim text.