Combinational superconducting gate circuit

A method for performing a logic operation, the method comprising:

• providing a reciprocal quantum logic (RQL) clock signal to a combinational superconducting gate circuit;
• providing a plurality of logic input signals to a respective plurality of input Josephson transmission line (JTL) segments of an input stage, the input JTL segments corresponding to a respective plurality of logical inputs of the superconducting gate circuit, each of the logic input signals corresponding to a presence of an RQL pulse in a first logic state and an absence of the RQL pulse in a second logic state, each of the logical inputs being separately weighted in importance based on circuit characteristics associated with each of the respective input JTL segments;
• propagating an output RQL pulse from an output of the combinational superconducting gate in a first output logic state associated with a logic operation in response to triggering of a decision Josephson junction of a logic operation stage;
• and
• propagating no output RQL pulse from the output of the combinational superconducting gate in a second output logic state associated with the logic operation in response to not triggering the decision Josephson junction of the logic operation stage;
• wherein the first and second output logic states of the logic operation are provided in response to the respective first or second logic states associated each of the logic input signals and based on the separately weighted logical inputs.