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US 2026/0254419 A1Published application
Bias circuit for class c amplifiers
AssigneeQUALCOMM Incorporated
InventorsSunbo SHIM, Muslum Emir AVCI, Jing-Hwa CHEN, Antonino SCUDERI
Life of this patent
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Abstract
Bias circuits are provided for biasing an amplifier transistor in load-modulated amplifiers such as a class C amplifier. In a first bias circuit, a current source drives a reference current into a first node coupled to a second node through a first resistor. The first node couples to a collector of a first bipolar junction transistor and to a base of a second bipolar junction transistor. The second node coupled to a base of a third bipolar junction transistor.
Claims20
An apparatus, comprising:
- a bias circuit, the bias circuit including:
- a current source configured to drive a reference current into a first node;
- a first bipolar junction transistor coupled between the first node and ground;
- a first resistor coupled between the first node and a second node;
- a second resistor;
- a second bipolar junction transistor having a collector coupled to the second node, a base coupled to the first node, and an emitter coupled to ground through the second resistor;
- and
- a third bipolar junction transistor having a base coupled to the second node;
- and
- an amplifier including a fourth bipolar junction transistor, wherein an emitter of the third bipolar junction transistor is coupled to a base of the fourth bipolar junction transistor to bias the fourth bipolar junction transistor.
7 more elements
An apparatus, comprising:
- a bias circuit, the bias circuit including:
- a current source configured to drive a reference current into a first node;
- a first resistor coupled between the first node and a second node;
- a first bipolar junction transistor coupled between the second node and ground;
- a second bipolar junction transistor having a base coupled to the first node and a collector coupled to the second node;
- a second resistor coupled in series with a third resistor between a collector of the second bipolar junction transistor and ground, wherein a node between the second resistor and the third resistor couples to a base of the first bipolar junction transistor;
- and
- a third bipolar junction transistor having a base coupled to the second node;
- and
- an amplifier including a fourth bipolar junction transistor, wherein an emitter of the third bipolar junction transistor is coupled to a base of the fourth bipolar junction transistor to bias the fourth bipolar junction transistor.
7 more elements
A method of biasing, comprising:
- conducting a current from a current source into a first node coupled to a collector of a first bipolar junction transistor and to a base of a second bipolar junction transistor to charge the first node;
- conducting a portion of the current from the first node through a resistor to a second node coupled to a collector of the second bipolar junction transistor to charge the second node to a base voltage;
- biasing a base of a third bipolar junction transistor with the base voltage to develop a bias voltage at an emitter of the third bipolar junction transistor;
- and
- biasing a base of a fourth bipolar junction transistor with the bias voltage.
2 more elements
Dependencies are inferred from the claim text.