Memory devices and memory systems
AssigneeFtmos, LLC
InventorSuresh Rajan
Life of this patent
Estimating the term…
Abstract
A memory system including a controller communicatively coupled to one or more memory devices is operable to provide improved one or more attributes, such as power, performance, latency, bandwidth, reliability, manufacturability, yield, cost, capacity, etc.
Claims134
An apparatus, comprising:
- a memory device including an array of bit cells arranged in rows and columns;
- and
- circuitry in communication with the memory device, the circuitry operating a first portion of the bit cells of the array and a second portion of the bit cells of the array, where the operation of the first portion of bit cells overlaps the operation of the second portion of bit cells.
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An apparatus, comprising:
- a memory device including an array of bit cells arranged in rows and columns;
- and circuitry in communication with the memory device, the circuitry operating to connect a first portion of the bit cells of the array to global bit lines and operating to isolate a second portion of the bit cells of the array from the global bit lines.
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A system, comprising:
- a memory sub-system including a controller communicatively coupled to one or more memory devices;
- wherein the memory sub-system is configured such that a first portion of the one or more memory devices and a second portion of the one or more memory devices may be operable overlapping each other.
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An apparatus, comprising:
- a memory device including an array of bit cells arranged in rows and columns;
- and
- circuitry in communication with the memory device, the circuitry configuring at least a portion of the bit cells of the array into a plurality of regions by assigning region identifiers to at least a portion of the bit cells of the array based on one or more aspects of the memory device, such that one or more bit cells with a first region identifier is remapped to a first region and one or more bit cells with a second region identifier is remapped to a second region.
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A method, comprising:
- at a memory device including an array of bit cells arranged in rows and columns:
- configuring at least a portion of the array of bit cells into a plurality of regions, by assigning region identifiers to at least a portion of the bit cells of the array based on one or more aspects of the memory device;
- remapping one or more bit cells with a first region identifier to a first region;
- and
- remapping one or more bit cells with a second region identifier to a second region.
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A system, comprising:
- a memory sub-system including a controller communicatively coupled to one or more memory devices;
- wherein the memory sub-system is configured such that at least a portion of the one or more memory devices is configured into multiple regions and information is communicated between the controller and the one or more memory devices, resulting in an equalization of sizes of at least some of the multiple regions in the one or more memory devices.
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An apparatus, comprising:
- a memory device including an array of bit cells arranged in rows and columns;
- and
- circuitry in communication with the memory device, the circuitry repairing at least a portion of the bit cells of the array by assigning valid identifiers to the portion of the bit cells of the array based on one or more aspects of the memory device.
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A method, comprising:
- at a memory device including an array of bit cells arranged in rows and columns:
- repairing at least a portion of the array of bit cells, by assigning repair identifiers to at least a portion of the bit cells of the array based on one or more aspects of the memory device;
- replacing one or more bit cells with one or more other bit cells.
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A system, comprising:
- a memory sub-system including a controller communicatively coupled to one or more memory devices;
- wherein the memory sub-system is configured such that information is communicated between the controller and the one or more memory devices, resulting in a repair of the one or more memory devices.
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An apparatus, comprising:
- a memory device including an array of bit cells arranged in rows and columns;
- and
- circuitry configuring at least a portion of the bit cells of the array into a plurality of regions based on one or more aspects of the memory device.
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A method, comprising:
- at a memory device including an array of bit cells arranged in rows and columns:
- configuring at least a portion of the array of bit cells into a plurality of regions based on one or more aspects of the memory device;
- remapping one or more bit cells from a first region to a second region;
- and
- restoring one or more bit cells from a second region back to a first region.
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An apparatus, comprising:
- a memory device including an array of bit cells arranged in rows and columns, and configured into a plurality of regions, such that a first region and a second region are separated by a guard band.
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An apparatus, comprising:
- a memory device including an array of bit cells arranged in rows and columns;
- and
- circuitry in communication with the memory device, the circuitry configured to apply a second voltage to a second conductor when a first voltage is applied to a first conductor during an operation of the memory device.
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An apparatus, comprising:
- a memory device including an array of bit cells arranged in rows and columns;
- and
- circuitry configured to remap a first plurality of bit cells from a first address to a second address, and remap a second plurality of bit cells from a second address to a first address.
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A system, comprising:
- a memory sub-system including a controller communicatively coupled to one or more memory devices;
- wherein the memory sub-system is configured such that at least a portion of the one or more memory devices is configured into multiple regions and information is communicated between the controller and the one or more memory devices, resulting in a plurality of bit cells being remapped from a first region to a second.
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A system, comprising:
- a memory sub-system including a controller communicatively coupled to one or more memory devices;
- wherein the memory sub-system is configured such that at least a portion of the one or more memory devices is configured into multiple regions separated by guard bands and information is communicated between the controller and the one or more memory devices, resulting in a refresh of a plurality of bit cells in a first region.
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A system, comprising:
- a memory sub-system including a controller communicatively coupled to one or more memory devices;
- wherein the memory sub-system is configured such that information is communicated between the controller and the one or more memory devices, resulting in a second voltage being applied to a second conductor when a first voltage is applied to a first conductor in one or more memory devices.
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A system, comprising:
- a memory sub-system including a controller communicatively coupled to one or more memory devices;
- wherein the memory sub-system is configured such that information is communicated between the controller and the one or more memory devices, resulting in a first plurality of bit cells being mapped from a first address to a second address and a second plurality of bit cells being mapped from a second address to a first address.
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An apparatus, comprising:
- a memory device including an array of bit cells arranged in rows and columns, wherein a row of bit cells includes one or more clamping transistors.
A system, comprising:
- a memory sub-system including a controller communicatively coupled to one or more memory devices;
- wherein the memory sub-system is configured such that information is communicated between the controller and the one or more memory devices, resulting in one or more conductors in the one or more memory devices being clamped to a signal.
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An apparatus, comprising:
- a memory device including an array of bit cells arranged in rows and columns;
- and
- circuitry remapping at least a portion of the bit cells of the array based on at least a portion of data written to the at least a portion of the bit cells.
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Dependencies are inferred from the claim text.