Memory array

Abstract

Provided is a memory array. The memory array includes at least one main array and at least one dummy array, the main array is adjacent to the dummy array, at least one resistive memory cell of the dummy array shares a same bit line with at least one resistive memory cell of an adjacent main array; and the size of the at least one resistive memory cell of the dummy array is greater than that of the at least one resistive memory cell of the adjacent main array. The larger size of the resistive memory cell corresponds to lower forming voltage, making it easier to change from a high resistance state to a low resistance state. As such, the initial state of the resistive memory cell in the main array can be in the high resistance state, thereby improving the yield of the memory array.

Dependencies are inferred from the claim text.