Display driver integrated circuit structure

A display driver integrated circuit structure, comprising:

• a first chip comprising first semiconductor devices, wherein the first semiconductor devices comprise a scan driver, a data driver, a gamma adjuster, a power circuit, a one-time programmable (OTP) memory, a multiple-time programmable (MTP) memory, a digital input-output (I/O) circuit, an analog I/O circuit, and a power I/O circuit;
• and
• a second chip bonded to the first chip and comprising second semiconductor devices, wherein the second semiconductor devices comprise a panel display controller, a power controller, a high-speed interface controller, a high-speed interface receiver, a high-speed interface command decoder, a low-speed interface controller, a low-speed interface receiver, a low-speed interface command decoder, a register read controller, a register write controller, a static random access memory (SRAM) controller, a SRAM bit-cell, an OTP memory controller, a MTP memory controller, an OTP memory bit-cell, a MTP memory bit-cell, a shift register of the scan driver, a shift register of the data driver, a latch of the scan driver, and a latch of the data driver.