System and method for recreating silicon behavior of system on chip

A method for recreating silicon behavior of a System on Chip (SoC), the method comprising:

• receiving silicon dump data associated with one or more masters of the SoC and a Network on Chip (NoC) of the SoC;
• generating, using one or more traffic generators, traffic injectable into the NoC, based on the silicon dump data;
• controlling one or more memory access latencies associated with the traffic, based on one or more pre-configured master-corresponding latency values;
• and
• recreating the silicon behavior of the SoC by executing the traffic with the controlled one or more memory access latencies.

A device for recreating silicon behavior of a System on Chip (SoC), the device comprising:

• one or more traffic generators configured to generate traffic injectable into a Network on Chip (NoC) of the SoC based on silicon dump data;
• one or more processors comprising processing circuitry;
• and
• a memory storing instructions,
• wherein the instructions, when executed by the one or more processors individually or collectively, cause the device to:
• receive the silicon dump data associated with one or more masters of the SoC and the NoC;
• control one or more memory access latencies associated with the traffic based on one or more pre-configured master-corresponding latency values;
• and
• recreate the silicon behavior of the SoC by executing the traffic with the controlled one or more memory access latencies.